The present invention relates in general to microelectronic elements such as semiconductor chip assemblies, and more particularly, to flexible leads for use in such microelectronic elements, as well as methods of manufacturing same.
Semiconductor chips typically are connected to external circuitry through contacts on the surface of the chip. The contacts may be disposed in a grid on the front surface of the chip or in elongated rows extending along the edges of the chip""s front surface. Each such contact must be connected to an external circuit element such as a circuit trace on a supporting substrate or circuit panel. In the conventional wire bonding process, the back surface of the chip is physically mounted on the substrate. A bonding tool bearing a fine wire is engaged with an individual contact on the face surface of the chip so as to bond the wire to the contact. The tool is then moved to a contact pad of the circuit on the substrate, while dispensing wire through the tool, until the tool engages the contact pad on the substrate and the wire is bonded thereto. This process is repeated for each contact.
In a tape automated bonding process, a dielectric supporting tape is provided with a hole slightly larger than the chip. Metallic leads are provided on the dielectric tape are cantilevered into the hole in the tape. An inner end of each lead projects inwardly beyond the edge of the hole. These plural leads are arranged side-by-side in rows. Each row of contacts on the chip is aligned with one such row of leads. The inner ends of the leads are bonded to the contacts of the chip by ultrasonic or thermocompression bonding. The outer ends of the leads are connected to the external circuitry.
The rapid evolution of the semiconductor art has created continued demand for incorporation of progressively greater numbers of contacts and leads in a given amount of space. U.S. Pat. No. 5,489,749, the disclosure of which is hereby incorporated by reference herein, offers one solution. As disclosed in certain embodiments of the patent, a semiconductor chip connection component may include a plurality of electrically conductive leads and may also include a support structure such as a flexible, dielectric film with a compliant, typically elastomeric underlayer disposed beneath the flexible film. Each such lead desirably is connected to a terminal disposed on the surface of the support structure. A connection section of each lead extends across a gap such as in the nature of a slot in the support structure. A first end of each connection section, connected to one of the terminals, is permanently attached to the support structure, whereas the opposite second end of the connection section is releasably attached to the support structure. For example, the second end of each connection section may be connected through a frangible section connecting the second end to a bus structure anchored on the support structure.
In certain processes disclosed in the ""749 Patent, the connection component is juxtaposed with the chip so that the support structure, and preferably a compliant layer thereof, overlies the contact bearing surface of the chip and so that the gap or slot in the support structure is aligned with a row of contacts on the chip. This process serves to align each connection section with a contact on the chip. After placement of the connection component on the chip, each lead is engaged by a bonding tool. The bonding tool moves downwardly towards the surface of the chip. As the bonding tool moves downwardly, it disengages the second end of each lead connection section from the support structure, as by breaking the frangible section of the lead, and moves the connection section downwardly into engagement with the chip contact. At the same time, guide surfaces on the bottom of the bonding tool engage the connection section and guide it into more precise alignment with the associated contact. The bonding tool then bonds the connection section to the contact.
The end supported lead bonding processes according to the ""749 Patent offer numerous advantages. Because each lead is supported at both ends prior to bonding, it can be maintained in position until it is captured by the bonding tool. The bonding tool will reliably capture the correct lead, and hence there is little chance that an incorrect lead will be bonded to a contact. Moreover, the products resulting from the disclosed processes allow free movement of the terminals on the support structure relative to the chip after connection, both in the X and Y directions, parallel to the chip surface, and in the Z or compliance direction perpendicular to the chip surface. Thus, the assembly can be readily tested by engaging a multiple probe test fixture with the terminals. When the terminals on the support structure are bonded to contact pads of a substrate, such as by solder bonding or other processes, the assembly can compensate for differential thermal expansion between the chip and the substrate, such as by flexing of the leads and deformation of the flexible support structure.
Certain components and processes disclosed in the ""749 Patent can be used to fabricate microelectronic elements such as semiconductor chip assemblies with closely spaced leads. Merely by way of example, rows of connection sections may be provided side-by-side at center-to-center spacing of about 100 micrometers or less, and may be successfully bonded to the contacts of the chip. Additional improvements in the bonding structures and techniques, as set forth in the commonly assigned U.S. Pat. Nos. 5,398,863 and 5,491,302, the disclosures of which are hereby incorporated by reference herein, still further facilitate bonding of closely spaced leads and formation of reliable assemblies even where the leads are extremely small, using the basic techniques set forth in the ""749 Patent.
Connection components typically have a reduced fatigue life. It is therefore desirable to provide leads with a structure which reinforces the lead, particularly in the fatigue susceptible regions of the lead. The most fatigue susceptible regions are those regions which are most distorted in the fabrication of the component, for example, in the shoulder region and heel region. Reinforcing at least these regions enhances the fatigue life of the connection component and completed assembly. It is also desirable to provide a lead structure which in addition to being reinforced against fatigue, promotes more efficient coupling of energy between the bonding tool and the bond interface between the bottom of the lead and the chip contact. This in turn allows reduced bonding force, bonding energy and/or bonding time, or provides a strong bond with the same force, energy and time so that connection components can be fabricated more economically.
In certain structures taught in co-pending U.S. patent application Ser. No. 09/179,273 filed on Oct. 27, 1998 entitled Layered Lead Structures, the disclosure of which is incorporated herein by reference, a connection component includes flexible leads incorporating a structural material such as copper, gold, alloys of these metals or other metals. Each lead is provided with a thin layer of a fatigue resistant alloy, such as the alloys commonly referred to as a shape memory alloys. The fatigue resistant alloy preferably is provided on the bonding or bottom side of the lead which is bonded to a contact during use of the component.
Most preferably, the layer of fatigue resistant alloy is provided at least in the bond region, i.e., the region of the lead which is bonded to the contact when the component is used to make connections with a microelectronic element. In particular, the fatigue resistant material is provided in the region of the lead which forms the xe2x80x9cheelxe2x80x9d of the bond. A layer of a readily bondable material such as gold, palladium or other metal compatible with the contact to which the lead is to be bonded is applied on the bottom or bond side of the lead covering the fatigue resistant alloy at least in the area of the lead which will engage the contact during use. The lead structures according to certain embodiments of these co-pending applications are asymmetrical, in that the fatigue resistant alloy and bondable metal are disposed only on the bottom side of the structural metal.
Another flexible lead for use in a microelectronic connection component as disclosed in the ""273 application is provided with an asymmetrical distribution of bonding metal at least in the bond region. The lead incorporates a layer of a structural metal, desirably copper, copper based alloy or other relatively low cost metal. A first layer of a readily bondable metal such as gold or gold based alloy (e.g., an alloy containing about 50% gold or more) or palladium is provided on the bottom surface of the structural metal layer. The top surface of the structural metal layer may be devoid of the bonding metal in the bond region or else may have a second layer of bonding metal which is thinner than the first layer of bonding metal. Typically, the first layer of bonding metal is thinner than the structural metal.
A layer of a barrier metal such as nickel or a nickel based alloy which is adapted to retard alloying of the structural metal and the bonding metal by diffusion optionally may be provided between the structural metal layer and the first layer of bonding metal. The barrier metal layer typically is thinner than the first layer of bonding metal and may include a fatigue resistant alloy. A similar barrier layer can be provided between the structural metal and the second layer of bonding metal, if such second layer is used. The leads typically are provided on a support structure such as a dielectric layer.
The disclosure of co-pending U.S. patent application Ser. No. 08/560,272, filed on Nov. 21, 1995 entitled A Structure and Method for Making a Compliant Lead for a Microelectronic Device is hereby incorporated by reference herein. The ""272 application discloses a method of treating a lead in a chip package. A conductive lead is positioned such that it extends across a gap in a dielectric substrate and is secured at either end to a first surface of the substrate. Directed energy is then applied to a desired portion of the surface of the lead within the gap. As a result of the application of energy, a surface layer of the lead is recrystallized thereby creating a fine grain, dense surface layer of lead material. Surface contaminants may be vaporized and contaminants at the grain boundaries of the recrystallized surface layers may be driven away from the grain boundaries such that a treated lead is more ductile and has better resistance to thermal cycling after the lead has been attached to a chip contact.
Notwithstanding the above improvements in the construction of fatigue resistant leads for connection components, it can be appreciated that there is still the desirability of providing additional improvements in the construction of flexible leads for use in microelectronic elements such as semiconductor chip assemblies and the like which address the aforementioned desirable features for such leads.
In accordance with one embodiment of the present invention there is described a lead having a bond region adapted for connection to a microelectronic element. The lead includes a first layer of a metal having top and bottom surfaces, a second layer of the metal on the top surface of the first layer at least within the bond region, the metal in the first layer having a hardness greater than the hardness of the metal in the second layer.
The hardness of the metal layers is controlled by depositing the metal layers having different grain size. The resulting lead may also be coated with a bonding material along all or a portion of the lead. In accordance with the preferred embodiment, the metal layers are copper while the bonding material is gold.
In accordance with another embodiment of the present invention there is described a microelectronic component having a supporting structure and at least one lead connected to the supporting structure. The lead includes a bond region, a first layer of a metal having top and bottom surfaces, a second layer of the metal on the top surface of the first layer at least within the bond region, the metal in the first layer having a hardness greater than the hardness of the metal in the second layer.
In accordance with another embodiment of the present invention there is described a method of making an electrical connection to a microelectronic component having at least one contact. The method includes the steps of juxtaposing a connection component with a microelectronic component, the connection component having a supporting structure and at least one lead connected to the supporting structure, the lead including a bond region adapted to be aligned with the contact, a first layer of a metal having top and bottom surfaces, a second layer of the metal on the top surface of the first layer at least within the bond region, the metal in the first layer having a hardness greater than the hardness of the metal in the second layer and bonding the bond region of the lead to the contact on the microelectronic component.
In accordance with another embodiment of the present invention there is described a method of making a lead having a bond region. The method includes the steps of depositing a first layer of a metal having top and bottom surfaces, depositing a second layer of the metal onto the top surface of the first layer at least within the bond region, controlling the steps of depositing the first and second layers such that the grain size of the metal in the first layer is smaller than the grain size of the metal in the second layer.